In order to analyze the operation states of the hardware of a processing apparatus such as a computer, a variety of techniques have been developed.
For example, a system in which a plurality of units such as a performance monitor (a PM circuit), a central processing unit (CPU), and an input/output unit are connected to a data bus has been developed. In such a system, the PM circuit detects an event to be monitored and stores the result of monitoring in a storage area provided in the PM circuit. In addition, a system has been developed that includes a comparator register and an interrupting line so that an interruption of a processor occurs when a counter value is equal to a predetermined value. Furthermore, in a CPU performance profiling called a hardware monitor incorporated in an instruction processor of an information processing apparatus, a function of generating an interruption when a target event occurs a number of times more than a predetermined threshold value has been developed.
For example, the following Patent Documents describe techniques of analyzing a hardware operation state:
Japanese National Publication of International Application No. 2006-524375,
Japanese Laid-open Patent Publication No. 2005-339107,
Japanese Laid-open Patent Publication No. 08-30494,
Japanese Laid-open Patent Publication No. 2005-215816,
Japanese Laid-open Patent Publication No. 2007-249534, and
Japanese Laid-open Patent Publication No. 2007-272692.
Existing processing apparatuses may determine whether the expected performance is achieved by monitoring the instruction execution time and the number of cache misses using a performance analyzer or a performance monitor. However, in order to improve the performance of the processing apparatus when a user program is executed and the expected performance is not achieved, it is difficult to use existing performance analyzers. For example, a user may not know the reason why the processing apparatus does not operate as expected only using, for example, the number of events.